The present invention relates to DC offset calibration. More specifically, the invention relates to mechanisms for reducing a DC offset voltage associated with an amplifier.
Amplifiers are used in various applications. In some applications, an audio amplifier includes a differential amplifier at its power stage for driving a loudspeaker coupled to the power stage. Such a differential power stage receives differential inputs, and, based on the inputs, drives the loudspeaker. To provide differential inputs to the differential power stage, a comparator having a pair of differential inputs and a pair of differential outputs may be used.
For example, outputs P and N of the (non-hysteretic) comparator are at high and low levels, respectively, when a voltage at an input P of the comparator is higher than a voltage at an input N of the comparator. Conversely, the outputs P and N are at low and high levels, respectively, when a voltage at an input P is lower than a voltage at an input N. In an ideal state, when the inputs P and N are at exactly the same voltage, the outputs P and N would be precisely at the average level of the high and low levels. In this ideal state, the comparator and circuitry associated with the comparator are completely balanced, and symmetric with respect to the two differentially driven inputs/outputs.
However, in reality, a comparator and circuitry associated with the comparator (e.g., a high-gain operational amplifier coupled to the comparator) have a natural tendency to set the outputs P and N at the high and low levels, respectively, or at the low and high levels, respectively, due to intrinsic asymmetries, however small. By way of example, in the above example, when the input P voltage is slightly higher than the input N voltage, the output P may be at the low level due to the tendency caused by the unbalanced or asymmetric circuit parameters. Typically, errors in parameters of various circuit elements, such as operational amplifiers and resistors, cause this imbalance with respect to the two differential inputs/outputs.
The unbalanced condition of the differential amplifier may generate a DC offset voltage at its output ports when it amplifies the input signal in a normal operating mode. In other words, even a small tendency to set one output at high and another output at low while the inputs are balanced (equal) may result in a residual DC component at the outputs in the normal operation mode.
The DC offset voltage causes unnecessary power dissipation during the normal operation mode. Further, the DC offset voltage generates a popping or clicking sound when the output of the amplifier is unmuted. This popping or clicking sound results from the voltage step which occurs when the amplifier abruptly transitions between applying no forcing function upon the load to applying the DC offset voltage.
In view of the above, it would be desirable to provide apparatus and methods for reducing a DC offset in an amplifier, thereby substantially eliminating the popping sound when the amplifier is unmuted, and reducing power dissipation due to the DC offset. The present invention addresses these needs by reducing or substantially canceling a DC offset voltage associated with a differential amplifier.
According to the present invention, a differential amplifier has first and second outputs and first and second supply rails. The differential amplifier further includes offset cancellation circuitry. The offset cancellation circuitry is operable during a calibration mode to generate an offset cancellation signal when the first and second outputs are both coupled to a calibration voltage between the first supply rail and the second supply rail. The differential amplifier cancels at least a part of an offset voltage associated with the first and second outputs during a normal operation mode based on the offset cancellation signal.
Alternatively, according to the present invention, a differential amplifier has first and second outputs and first and second supply rails. The differential amplifier further includes offset cancellation circuitry. The offset cancellation circuitry is operable during a calibration mode to generate a first offset cancellation signal when the first and second outputs are coupled to the first supply rail, and a second offset cancellation signal when the first and second output are coupled to the second supply rail. The offset cancellation circuitry is also operable during the calibration mode to generate a third offset cancellation signal by averaging the first and second offset cancellation signals. The differential amplifier cancels at least a part of an offset voltage associated with the first and second outputs during a normal operation mode based on the third offset cancellation signal.
In a specific embodiment, the first and second supply rails supply a power supply voltage and a ground voltage, respectively, and the calibration voltage is substantially an average of the power supply voltage and the ground voltage.
In another embodiment, the differential amplifier further includes a signal processor block, comparator circuitry, and a switching amplifier. The signal processor block is operable to receive an input of the differential amplifier and the offset cancellation signal, and generate an output signal. The comparator circuitry is operable to convert the output signal into a binary signal. The switching amplifier is operable to amplify the binary signal, and generate the first and second outputs.
In still another embodiment, the differential amplifier includes a plurality of sets of the signal processor block, the comparator circuitry, and the switching amplifier corresponding to a plurality of channels. The offset cancellation circuitry may be operable to generate a plurality of the offset cancellation signals corresponding to the plurality of channels.
In still another embodiment, the differential amplifier includes a successive approximation type analog-to-digital converter, and a digital-to-analog converter. The successive approximation type analog-to-digital converter is operable to generate offset compensation data based on the offset voltage. The digital-to-analog converter is operable to receive the offset compensation data, generate an offset compensation voltage based on the offset compensation data, and apply the offset compensation voltage to an input of the differential amplifier.
According to another aspect of the invention, a method for reducing an offset voltage of a differential amplifier is provided. The differential amplifier includes first and second outputs and first and second supply rails. The method generates an offset cancellation signal when the first and second outputs are both coupled to a voltage between the first supply rail and the second supply rail during a calibration mode of the differential amplifier. The method applies the offset cancellation signal to an input of the differential amplifier for facilitating at least partial cancellation of the offset voltage associated with the first and second outputs during a normal operation mode of the differential amplifier.
According to still another aspect of the invention, the method generates a first offset cancellation signal when the first and second outputs are coupled to the first supply rail, and a second offset cancellation signal when the first and second output are coupled to the second supply rail during a calibration mode of the differential amplifier. The method generates a third offset cancellation signal by mathematically combining the first and second offset cancellation signals. The method applies the third offset cancellation signal to an input of the differential amplifier for facilitating at least partial cancellation of the offset voltage associated with the first and second outputs during a normal operation mode of the differential amplifier.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.